 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| r01ds0186ej0120 rev.01.20 page 1 of 35 sep 10, 2012 datasheet sh74593 renesas mcu 1. overview the sh7459 group is a single-chip risc (reduced instruction set computer) microcontroller based on a renesas original risc cpu core. basically the sh7459 group is the same as the sh7456 group. please refer to sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 1.1 shows the differences between the sh7456 group and the sh7459 group. * henceforth, the bold letter portion (shaped portion) shows a difference from sh7456 group. table 1.1 products group product model cpu frequency memory capacity package flexray operating temperature (ta) sh7459 sh74593 r5f74593lbg 240 mhz rom: 1.5 mbytes il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes yes -40 to + 105 c sh7455 sh74552 r5f74552kbg yes sh7456 sh74562 r5f74562kbg 160mhz no -40 to +125c sh7457 sh74572 r5f74572lbg 240mhz rom: 1mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes prbg0176ga-a yes -40 to +105c 2. details this section shows the details of the differen ce from sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 2.1 sh ows the difference between the sh74562 and the sh74593. table 2.1 difference between sh74562 and sh74593 page description 1-1 ? 1.1 features product superhyway ram (shwyram) capacity sh74562 256 kbytes sh74593 512 kbytes ? table 1.1 specifications overview: descriptions of rom product rom capacity sh74562 1-mbytes sh74593 1.5 -mbytes 1-4 ? table 1.1 specifications overview: descriptions of ram product ram capacity sh74562 256-kbytes sh74593 512 -kbytes 1-4 ? table 1.1 specifications overview: descriptions of cpg product cpu clock (ick) sh74562 160 mhz maximum sh74593 240 mhz maximum r01ds0186ej0120 rev.01.20 sep 10, 2012
sh74593 2. details r01ds0186ej0120 rev.01.20 page 2 of 35 sep 10, 2012 page description 1-6 ? table 1.1 specifications overview: descriptions of flexray product channels of flexray sh74562 none: sh7456 group sh74593 two channels : sh7459 group ? table 1.1 specifications overview: descriptions of operating temperature product operating temperature sh74562 ta = ?40c to +125c sh74593 ta = ?40c to + 105 c 1-7 ? table 1.2 products product model rom capacity shwyram capacity flexray sh74562 r5f74562kbg 1 mbyte 256 kbytes no sh74593 r5f74593lbg 1.5 mbytes 512 kbytes yes please refer to appendix a. 1-8 ? figure 1.1 block diagram product sh-4a core clock rom capacity shwyram capacity sh74562 sh-4a core (160 mhz maximum) rom (1 mbyte) shwyram (256 kbytes) sh74593 sh-4a core ( 240 mhz maximum) rom ( 1.5 mbytes) shwyram ( 512 kbytes) 1-9 1-15 ? figure 1.2 pin arrangement (top transparent view) ? table 1.3 pin functions of pin a6 product a6 pin sh74562 vcc sh74593 vss please refer to appendix b. 11-2 ? figure 11.2 address space (p0/u0 area): description s of 29-bit physical address space (single chip) product rom capacity (start address ? last address) shwyram capacity (start address ? last address) sh74562 1 mbyte (h?0000 000 0 ? h?000f ffff) 256 kbytes(h?1800 0000 ? h?1803 ffff) sh74593 1.5 mbytes (h?0000 0000 ? h?0017 ffff ) 512 kbytes(h?1800 0000 ? h?1807 ffff ) please refer to appendix c.1. 11-3 ? figure 11.3 address space (p1 area): descriptions of 29-bit physical address space (single chip) product rom capacity (start address ? last address) shwyram capacity (start address ? last address) sh74562 1 mbyte (h?8000 000 0 ? h?800f ffff) 256 kbytes(h?9800 0000 ? h?9803 ffff) sh74593 1.5 mbytes (h?8000 0000 ? h?8017 ffff ) 512 kbytes(h?9800 0000 ? h?9807 ffff ) please refer to appendix c.2. 11-4 ? figure 11.4 address space (p2 area): descriptions of 29-bit physical address space (single chip) product rom capacity (start address ? last address) shwyram capacity (start address ? last address) sh74562 1 mbyte (h?a000 0000 ? h?a00f ffff) 256 kbytes(h?b800 0000 ? h?b803 ffff) sh74593 1.5 mbytes (h?a000 0000 ? h?a017 ffff ) 512 kbytes(h?b800 0000 ? h?b807 ffff ) please refer to appendix c.3. 11-5 ? figure 11.5 address space (p3 area): descriptions of 29-bit physical address space (single chip) product rom capacity (start address ? last address) shwyram capacity (start address ? last address) sh74562 1 mbyte (h?c000 0000 ? h?c00f ffff) 256 kbytes(h?d800 0000 ? h?d803 ffff) sh74593 1.5 mbytes (h?c000 0000 ? h?c017 ffff ) 512 kbytes(h?d800 0000 ? h?d807 ffff ) please refer to appendix c.4. sh74593 2. details r01ds0186ej0120 rev.01.20 page 3 of 35 sep 10, 2012 page description ? 12. rom product rom capacity sh74562 1 mbyte sh74593 1.5 mbytes ? 12.1 overview product area sh74562 when the user boot mat is select ed, the area from h?0000 8000 to h?000f ffff has an undefined value when read and both writing and erasing are disabled. sh74593 when the user boot mat is selected, the area from h?0000 8000 to h?0017 ffff has an undefined value when read and both writing and erasing are disabled. 12-1 ? figure 12.1 memory mat configuration in rom: descriptions of user mat product read : start address ? last address program/erase : start address ? last address sh74562 h?0000 0000 ? h?000f ffff h?fd80 0000 ? h?fd8f ffff sh74593 h?0000 0000 ? h?0017 ffff h?fd80 0000 ? h?fd97 ffff please refer to appendix d.1. sh74593 2. details r01ds0186ej0120 rev.01.20 page 4 of 35 sep 10, 2012 page description 12-1 12-2 ? 12.1 overview ? figure 12.2 block diagram of rom: descriptions of rom mat product capacity of user mat sh74562 1 mbyte sh74593 1.5 mbytes ? 12.1 overview : programming/erasing unit product number of 128-kbytes block sh74562 three blocks sh74593 seven blocks 12-3 ? figure 12.3 user mat and block allocation product name of 128-kbytes block sh74562 eb17 to eb19 sh74593 eb17 to eb23 added the following blocks block name read : start address ? last address program/erase : start address ? last address eb20 h?0010 0000 ? h?0011 ffff h?fd90 0000 ? h?fd91 ffff eb21 h?0012 0000 ? h?0013 ffff h?fd92 0000 ? h?fd93 ffff eb22 h?0014 0000 ? h?0015 ffff h?fd94 0000 ? h?fd95 ffff eb23 h?0016 0000 ? h?0017 ffff h?fd96 0000 ? h?fd97 ffff please refer to appendix d.2. 12-4 ? 12.1 overview : protection modes product description sh74562 this mcu supports two modes to protect memory against programming or erasure: hardware protection by the levels on the fwe and mode pins and software protection by the fentry0 bit or lock bit settings. the fentry0 bit enables or disables rom programming or erasure by the fcu. sh74593 this mcu supports two modes to protect memory against programming or erasure: hardware protection by the levels on the fwe and mode pins and software protection by the fentry1 and fentry0 bits or lock bit settings. the fentry1 and fentry0 bits enable or disable rom programming or erasure by the fcu. 12-7 ? 12.3.2 flash access status register (fastat) : description of romae bit product conditions for setting to ?1? sh74562 - a read access command is issued to rom read addresses h'0000 0000 to h'000f ffff while the fentryr register value is not h'0000. - an access command is issued to an address other than rom program/erase addresses h'fd80 0000 to h'fd8f ffff when the user boot mat is selected. sh74593 - a read access command is issued to rom program/erase addresses h'fd90 0000 to h'fd97 ffff while the fentry1 bit in the fentryr register is "1" in rom p/e normal mode. - an access command is issued to rom program/erase addresses h'fd90 0000 to h'fd97 ffff while the fentry1 bit in the fentryr register is "0". - a read access command is issued to rom read addresses h'0000 0000 to h'0017 ffff while the fentryr register value is not h'0000. - an access command is issued to an address other than rom program/erase addresses h'fd8f 0000 to h'fd80 7fff when the user boot mat is selected. please refer to appendix d.3. sh74593 2. details r01ds0186ej0120 rev.01.20 page 5 of 35 sep 10, 2012 page description ? 12.3.6 flash p/e mode entry register (fentryr) product description sh74562 to specify the p/e mode for the rom so that the fcu can accept commands, set the fentry0 bit to "1". sh74592 to specify the p/e mode for the rom so that the fcu can accept commands, set either of bits fentry1 and fentry0 to "1". 12-12 ? 12.3.6 flash p/e mode entry register (fentryr) : description of fekey bit product description sh74562 these bits enable or disable fentry0 bit m odification. the data written to these bits are not retained. these bits are always read as "0". h'aa: enable fentry0 bit modification. other than h'aa: disable fentry0 bit modification. sh74593 these bits enable or disable bit modification of fentry1 and fentry0. the data written to these bits are not retained. these bits are always read as "0". h'aa: enable bit modification of fentry1 and fentry0. other than h'aa: disable bit modification of fentry1 and fentry0. 12-12 ? 12.3.6 flash p/e mode entry register (fentryr) : description of fentry1 bit product r w description sh74562 0 0 rom p/e mode entry bit 1 this bit is not supported by the mcu. always write "0" to fentry1. sh74593 r w rom p/e mode entry bit 1 these bits specify the p/e mode for the eb20 to eb23 blocks of rom (read addresses: h'0010 0000 to h'0017 ffff; program/erase addresses: h'fd90 0000 to h'fd97 ffff). 0: the block of rom from eb20 to eb23 (0.5mbytes) is in read mode 1: the block of rom from eb20 to eb23 (0.5mbytes) is in p/e mode programming is enabled when the following conditions are all satisfied: - the fwe bit in the fpmon register is "1". - the frdy bit in the fstatr0 register is "1". - h'aa is written to the fekey bit in word access. [conditions for clearing to "0"] - the frdy bit in the fstatr0 register becomes "1" and the fwe bit in the fpmon register becomes "0". - this register is written to in byte access. - a value other than h'aa is written to the fekey bit in word access. - "0" is written to fentry1 while the write enabling conditions are satisfied. - the fentryr register is written to while the fentryr register is not h'0000 and the write enabling conditions are satisfied. [condition for setting to "1"] - "1" is written to the fentry1 bit while the write enabling conditions are satisfied and the fentryr register is h'0000. please refer to appendix d.4. 12-19 ? table 12.5 fcu command format: description of legend product ra: rom program/erase address sh74562 when the fentry0 bit is "1": an address in the range from h'fd80 0000 to h'fd8f ffff sh74593 when the fentry0 bit is "1": an address in the range from h'fd80 0000 to h'fd8f ffff when the fentry1 bit is "1": an address in the range from h'fd90 0000 to h'fd97 ffff sh74593 2. details r01ds0186ej0120 rev.01.20 page 6 of 35 sep 10, 2012 page description 12-20 ? figure 12.6 fcu mode transiti on diagram (rom-related modes) product transition from ?rom read mode? to ?rom p/e mode? sh74562 fentryr = h?0001 sh74593 fentryr = h?0001 or fentryr = h?0002 please refer to appendix d.5. 12-20 ? 12.6.2 conditions for fcu command acceptance : (1) rom read mode product description sh74562 this mcu switches to this mode when the fentry0 bit in the fentryr register is set to "0". sh74593 this mcu switches to this mode when both the fentry1 and fentry0 bits in the fentryr register are set to "0". 12-20 ? 12.6.2 conditions for fcu command acceptance : (2) rom p/e mode product description sh74562 the fcu enters this mode when the fentry0 bi t is set to "1". table 12.6 lists the commands that the fcu accepts. the high-speed rom readout operat ion cannot be used in this mode. although read access to locations h'fd80 0000 to h'fd8f ffff is illegal, undefined values will be returned. to read the rom data, the fcu must switch to rom read mode. if a peripheral-bus read access to a location from h'fd80 0000 to h'fd8f ffff is issued in the state where the fentry0 bit is "1", a rom access error will occur and the fcu will switch to the command- locked state. (see section 12.8.3, error protection.) sh74593 the fcu enters this mode when either the fentry1 or fentry0 bit is set to "1". table 12.6 lists the commands that the f cu accepts. the high-speed rom r eadout operation cannot be used in this mode. although read a ccess to locations h'fd80 0000 to h'fd97 ffff is illegal, undefined values will be returned. to read the rom da ta, the fcu must switch to rom read mode. if a peripheral-bus read access to a location from h'fd90 0000 to h'fd97 ffff is issued in the state where the fentry1 bit is "1", or if a peripheral-bus read access to a location from h'fd80 0000 to h'fd8f ffff is issued in the stat e where the fentry0 bit is "1", a rom access error will occur and the fcu will switch to the command-locked state. (see section 12.8.3, error protection.) 12-22 ? figure 12.7 command state transiti ons in rom read mode and p/e mode product transition from ?rom read mode? to ?rom p/e mode? sh74562 fentryr = h?0001 sh74593 fentryr = h?0001 or fentryr = h?0002 please refer to appendix d.6. 12-23 ? 12.6.3 fcu command usage : (1) met hods for switching to rom p/e mode product description sh74562 for an application to execute rom related f cu commands, it is necessary to set the fcu to rom p/e mode by setting the fentry0 bit in the fentry r register. (see section 12.6.2, conditions for fcu command acceptance.) to use rom related fcu commands, set the fentry0 bit to "1". see section 12.3.6, flash p/e mode entry register (fentryr) for the conditions for setting the fentry0 bit. sh74593 for an application to execute rom related f cu commands, it is necessary to set the fcu to rom p/e mode by setting bits fentry1 and fentry0 in the fentryr regist er. (see section 12.6.2, conditions for fcu command acceptance.) to use fcu commands for the first 1-mbyte and second 0.5-mbyte sections of rom, set bits fentry1 and fentry0 to the corresponding state . see section 12.3.6, flash p/e mode entry register (fentryr) for the conditions for setting bits fentry1 and fentry0 . sh74593 2. details r01ds0186ej0120 rev.01.20 page 7 of 35 sep 10, 2012 page description 12-23 ? figure 12.8 procedure for transition to rom p/e mode product specifies ?rom p/e mode? sh74562 to set fentry0 to 1 : write h?aa01 sh74593 to set fentry1 to 1 : write h?aa02 to set fentry0 to 1 : write h?aa01 please refer to appendix d.7. 12-24 ? 12.6.3 fcu command usage : (2) entering rom read mode product description sh74562 to enable high-speed rom read access over the superhyway bus, it is necessary to set the fcu to rom read mode by clearing the fent ry0 bit in the fentryr register. sh74593 to enable high-speed rom read access over the superhyway bus, it is necessary to set the fcu to rom read mode by clearing bits fentry1 and fentry0 in the fentryr register. 12-25 ? 12.6.3 fcu command usage : (3) programming product description sh74562 the addresses that can be specified in t he first to 131st cycles depend on the setting of the fentry0 bit in the fentryr register. an addre ss in the range from h'fd80 0000 to h'fd8f ffff is can be specified when the fentry0 bit is set to "1". if a command is issued while an illegal combination of the fentry0 bit value and ad dresses is specified, the fcu detects an error and enters command-locked state (see section 12.8.3, error protection). sh74593 the addresses that can be specified in the first to 131st cycles depend on the setting of bits fentry1 and fentry0 in the fentryr register. an address in the range from h'fd90 0000 to h'fd97 ffff is can be specified when the fentry1 bit is set to "1", or an address in the range from h'fd80 0000 to h'fd8f ffff is can be sp ecified when the fentry0 bit is set to "1". if a command is issued while an illegal combination of fentry1 and fentry0 bit values and addresses is specified, the fcu detects an erro r and enters command-locked state (see section 12.8.3, error protection). 12-33 ? 12.8.1 hardware protection : (1) protection through fwe pin product description sh74562 in this state,"1" cannot be written to the fentry0 bit in the fentryr register; that is, rom p/e mode cannot be entered, which prevents the rom from being programmed or erased. when the frdy bit is set to "1" and the fwe pin is "l" level, the fcu clears the fentry0 bit to disable rom programming and erasure. sh74593 in this state,"1" cannot be written to bits fentry1 and fentry0 in the fentryr register; that is, rom p/e mode cannot be entered, which prev ents the rom from being programmed or erased. when the frdy bit is set to "1" and the fwe pin is "l" level, the fcu clears bits fentry1 and fentry0 to disable rom programming and erasure. 12-33 ? 12.8.2 software protection : (1) fentryr protection product description sh74562 when the fentry0 bit is "0", the eb00 to eb19 blocks of rom (read addresses: h'0000 0000 to h'000f ffff, program/erase addresse s: h'fd80 0000 to h'fd8f ffff) goes to rom read mode. sh74593 when the fentry1 bit in the fentryr register is "0", the eb20 to eb23 blocks of rom (read addresses: h'0010 0000 to h'0017 ffff, program/erase a ddresses: h'fd90 0000 to h'fd97 ffff) goes to rom read mode. when the fentry0 bit is "0", the eb00 to eb19 blocks of rom (read addresses: h'0000 0000 to h'000f ffff, program/era se addresses: h'fd80 0000 to h'fd8f ffff) goes to rom read mode. sh74593 2. details r01ds0186ej0120 rev.01.20 page 8 of 35 sep 10, 2012 page description 12-34 ? table 12.7 error protection types product rom access error sh74562 - a read access command has been issued to addresses h'0000 0000 to h'000f ffff while the fentryr register value is not h'0000. sh74593 - a read access command has been issued to addresses h'fd90 0000 to h'fd97 ffff while fentry1 = "1" in rom p/e normal mode. - a read access command has been issued to addresses h'0000 0000 to h'0017 ffff while the fentryr register value is not h'0000. please refer to appendix d.8. 13-1 13-2 ? 13.1 overview ? figure 13.2 address space : descriptions of 29-bit physical address space (area 6) product shwyram capacity (start address ? last address) sh74562 256 kbytes(h ?1800 0000 ? h?1803 ffff) sh74593 512 kbytes(h?1800 0000 ? h?1807 ffff ) please refer to appendix e. 13-1 ? figure 13.1 block diagram of shwyram : descriptions of memory block product page number [capacity] sh74562 page 3 [64 kb] sh74593 page 7 [64 kb] 13-2 ? figure 13.2 address space product page sh74562 page 0 to page 3 sh74593 page 0 to page 7 added the following pages page address (29-bit physical address) page 4 h?1804 0000 ? h?1804 ffff page 5 h?1805 0000 ? h?1805 ffff page 6 h?1806 0000 ? h?1806 ffff page 7 h?1807 0000 ? h?1807 ffff please refer to appendix e. 14-1 ? table 14.1 relation between i nput frequency and input clock ? figure 14.1 block diagram of cpg product pll frequency multiplier (input to cpu) sh74562 x8. sh74593 x 12 . please refer to appendix f. 14-1 ? table 14.1 relation between i nput frequency and input clock product cpu clock(mhz) sh74562 160. sh74593 240 please refer to appendix f. 15-60 ? table 15.9 minimum of interrupt resp onse time: response time (minimum) product nmi irq peripheral module remarks sh74562 40icyc + s icyc 36icyc + s icyc 32icyc + s icyc when icyc:scyc: pcyc = 4:2:1 sh74593 55 icyc + s icyc 49 icyc + s icyc 43 icyc + s icyc when icyc:scyc: pcyc = 6 :2:1 please refer to appendix g. sh74593 2. details r01ds0186ej0120 rev.01.20 page 9 of 35 sep 10, 2012 page description 28-1 ? table 28.1 drii overview product access areas sh74562 all shwyram areas (up to 256 kbytes) sh74593 all shwyram areas (up to 512 kbytes) please refer to appendix h.1. 28-46 ? 28.3.23 drii address reload registers 0 and 1 ( driiadr0rld and driiadr1rld) : description of driadmrld bit product description sh74562 address bits 18 to 2 reload value (256-kbyte area) sh74593 address bits 18 to 2 reload value ( 512 -kbyte area) please refer to appendix h.2. 28-47 ? 28.3.24 drii address counters 0 and 1 (driiadr0 ct and driiadr1ct) : description of driadn bit product description sh74562 destination address bits 18 to 2 (256-kbyte area) sh74593 destination address bits 18 to 2 ( 512 -kbyte area) please refer to appendix h.3. 29-1 ? table 29.1 dro module overview product access area sh74562 shwyram area (256 kbytes) sh74593 shwyram area ( 512 kbytes) please refer to appendix i. 38-1 ? table 38.1 absolute maximum ratings product power dissipation (pd) sh74562 1000 mw ,ta = ?40c to +125c sh74593 1200 mw ,ta = ?40c to + 105 c please refer to appendix j.1. 38-1 ? table 38.1 absolute maximum ratings product operating temperature (topr) sh74562 ?40c to +125c sh74593 ?40c to + 105 c please refer to appendix j.1. 38-10 ? table 38.14 dc characteristics - supply current product core supply current (vdd power supply) sh74562 idd is 480 ma(maximum) ick = 160 mhz sh74593 idd is 560 ma(maximum) ick = 240 mhz please refer to appendix j.2. 38-11 ? 38.3 ac characteristics: descriptions of the timing conditions product the timing conditions of ac characteristics sh74562 ta = ?40c to +125c sh74593 ta = ?40c to + 105 c please refer to appendix j.3. sh74593 appendix a r01ds0186ej0120 rev.01.20 page 10 of 35 sep 10, 2012 appendix a section 1 overview 1.2 product line overview table 1.2 lists the products. table 1.2 products product model rom capacity ram capacity package flexray sh74552 r5f74552kbg yes sh74562 r5f74562kbg no sh74572 r5f74572lbg 1 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes yes sh74593 r5f74593lbg 1.5 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes prbg0176ga-a yes sh74593 appendix b r01ds0186ej0120 rev.01.20 page 11 of 35 sep 10, 2012 appendix b section 1 overview 1.4 pin arrangement figure 1.2 shows the pin arrangement. position o f pin a1 1 wdtovf# xtal md2 md0 md1 pllvcc extal nmi fwe pd3/ pdidata3 pd1/ pdidata1 pd4/ pdidata4 pd9/ pdidata9 pd8/ pdidata8 pd2/ pdidata2 pd10/ pdiwr pd7/ pdidata7 pd6/ pdidata6 pd0/ pdidata0 pd5/ pdidata5 pa0/ to00/ ddb00 pe15/ to27/ pslclr trst# asebrk#/ brkack tdi tdo tck tms reset# mpmd pf0/ crx0 pf1/ ctx0 pf4/ sda/ (crx3) pf5/ scl/ (ctx3) pg0/ mosi0/ to40 pg1/ miso0/ to41 pa2/ to02/ ddb02 pa1/ to01/ ddb01 pa4/ to04/ ddb04 pa3/ to03/ ddb03 pa6/ to06/ ddb06 pa5/ to05/ ddb05 pa8/ to10/ ddb08/ pslclkb pa7/ to07/ ddb07 pa10/ to12/ ddb10/ psldata0 pa9/ to11/ ddb09/ pslclka pa13/ to15/ ddb13/ psldata3 pa12/ to14/ ddb12/ psldata2 pa11/ to13/ ddb11/ psldata1 pb0/ pwmoff0/ dinb0 pb1/ pwmoff1/ dinb1 pc0/ to30/ mosi2/ (irq6) pc2/ to32/ rspck2/ dreq0 pc3/ to33/ ssl20/ irq0 pb3/ pwmoff3/ dinb3 pc5/ to35 pc14 pc6/ clkout/ to36 pllvss pg3/ to43/ ssl00/ (irq7) pg4/ irq2/ to44/ ssl01 pg2/ rspck0/ to42 vss (n.c.) vss vss (n.c.) vss vss vss vss vss vss vss vss avss vcc vss vss vcc vcc vdd vdd vdd vdd vss vcc vcc vss vss vss vss vss vss vcc vcc det3or5 vdd vdd vss vdd vss (n.c.) vdd vdd pl4/ tia10/ (tif0a) pl5/ tia11/ (tif0b) pl8/ tia14/ irq7/ dreq3 pl9/ tia15/ audrevt# pl6/ tia12/ (tif1a) ph8/ drod0/ (to30)/ ddc08/ rts2# ph9/ drod1/ (to31)/ ddc09/ cts2# ph2/ drod10/ to22/ ddc02/ tif1a ph5/ drod13/ to25/ ddc05/ tia01 ph10/ drod2/ (to32)/ ddc10 ph11/ drod3/ (to33)/ ddc11 pl2/ drowr pl3/ irq6 ph7/ drod15/ (to27)/ ddc07/ tia03 ph12/ drod4/ to34/ ddc12 ph13/ drod5/ (to35)/ ddc13 ph14/ drod6/ (to36)/ ddc14/ irq1 ph15/ drod7/ to37/ ddc15 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 23456789101112131415 123456789101112131415 pc1/ to31/ miso2 avss pm11/ ad0in11 pm13/ ad0in13 pm15/ ad0in15 pm10/ ad0in10 pm2/ ad0in2 pm12/ ad0in12 pm0/ ad0in0 pn1/ ad1in1 p n 0 / a d 1 i n 0 pn5/ ad1in5 pn4/ ad1in4 avcc (n.c.) avrefh avrefh avrefl avrefl avcc pj6/ crx3/ tif2a/ rxd2/ tia04 pj7/ ctx3/ tif2b/ txd2 pj11/ txd0/ ad0end pj12/ sck0/ tclkb/ (irq0) pj13/ rxd1/ miso1 pj10/ rxd0/ pwmoff4/ ad0trg# pj15/ sck1/ pspck1 pj14/ txd1/ mosi1 pj3/ ctx1/ ftxb/ rts0# pj2/ crx1/ frxb pj5/ ctx2/ ftxenb/ sck2 pj4/ crx2/ ftxena/ cts0# pj1/ (ctx0)/ ftxa pj0/ (crx0)/ frxa pm14/ ad0in14 pm6/ ad0in6 pm9/ ad0in9 pm8/ ad0in8 pm4/ ad0in4 avss avss avcc pk14/ audrsyn# pk5/ dinc4/ rxd3 pk13/ audrclk pk12/ audrd3 pk11/ audrd2 ph1/ drod9/ to21/ ddc01/ tif0b ph3/ drod11/ to23/ ddc03/ tif1b ph0/ drod8/ to20/ ddc00/ tif0a pk0/ irq5/ ssl10 ph4/ drod12/ to24/ ddc04/ tia00 ph6/ drod14/ to26/ ddc06/ tia02 p k 6 / t x d 3 pk8/ dreq2 pk10/ audrd1/ cts3# pk9/ audrd0/ rts3# figure 1.2 pin arrangement (top transparent view) sh74593 appendix c r01ds0186ej0120 rev.01.20 page 12 of 35 sep 10, 2012 appendix c appendix c.1 section 11 address space for details on the p0/u0 area to the p4 area, see figures 11.2 to 11.6. internal rom (1.5 mbyte) p0/u0 area (512 mbytes) single chip shwyram (512 kbytes) reserved reserved reserved reserved h'0000 0000 h'1fff ffff h'0017 ffff h'0018 0000 h'03ff ffff h'0400 0000 h'07ff ffff h'0800 0000 h'0bff ffff h'0c00 0000 h'0fff ffff h'1000 0000 h'13ff ffff h'1400 0000 h'17ff ffff h'1800 0000 h'1bff ffff h'1c00 0000 h'1807 ffff h'1808 0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 note: the cpu, dmac, audr, and other modules cannot access a reserved area. but the cpu can access area 7 as a control register area using the mmu. 32-bit virtual address space via cpu 29-bit physical address space figure 11.2 address space (p0/u0 area) sh74593 appendix c r01ds0186ej0120 rev.01.20 page 13 of 35 sep 10, 2012 appendix c.2 section 11 address space p1 area (512 mbytes) single chip shwyram (512 kbytes) internal rom (1.5 mbyte) reserved reserved reserved reserved h'8000 0000 h'9fff ffff h'8017 ffff h'8018 0000 h'83ff ffff h'8400 0000 h'87ff ffff h'8800 0000 h'8bff ffff h'8c00 0000 h'8fff ffff h'9000 0000 h'93ff ffff h'9400 0000 h'97ff ffff h'9800 0000 h'9bff ffff h'9c00 0000 h'9807 ffff h'9808 0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 note: the cpu, dmac, audr, and other modules cannot access a reserved area. 32-bit virtual address space via cpu 29-bit physical address space figure 11.3 address space (p1 area) sh74593 appendix c r01ds0186ej0120 rev.01.20 page 14 of 35 sep 10, 2012 appendix c.3 section 11 address space p2 area (512 mbytes) single chip shwyram (512 kbytes) internal rom (1.5 mbyte) reserved reserved reserved reserved h'a000 0000 h'bfff ffff h'a017 ffff h'a018 0000 h'a3ff ffff h'a400 0000 h'a7ff ffff h'a800 0000 h'abff ffff h'ac00 0000 h'afff ffff h'b000 0000 h'b3ff ffff h'b400 0000 h'b7ff ffff h'b800 0000 h'bbff ffff h'bc00 0000 h'b807 ffff h'b808 0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 note: the cpu, dmac, audr, and other modules cannot access a reserved area. 32-bit virtual address space via cpu 29-bit physical address space figure 11.4 address space (p2 area) sh74593 appendix c r01ds0186ej0120 rev.01.20 page 15 of 35 sep 10, 2012 appendix c.4 section 11 address space p3 area (512 mbytes) single chip shwyram (512 kbytes) internal rom (1.5 mbyte) reserved reserved reserved reserved h'c000 0000 h'dfff ffff h'c017 ffff h'c018 0000 h'c3ff ffff h'c400 0000 h'c7ff ffff h'c800 0000 h'cbff ffff h'cc00 0000 h'cfff ffff h'd000 0000 h'd3ff ffff h'd400 0000 h'd7ff ffff h'd800 0000 h'dbff ffff h'dc00 0000 h'd807 ffff h'd808 0000 area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 note: the cpu, dmac, audr, and other modules cannot access a reserved area. but the cpu can access area 7 as a control register area using the mmu. 32-bit virtual address space via cpu 29-bit physical address space figure 11.5 address space (p3 area) sh74593 appendix d r01ds0186ej0120 rev.01.20 page 16 of 35 sep 10, 2012 appendix d section 12 rom appendix d.1 12.1 overview ? two types of flash-memory mats address h'0000 0000 address h'0017 ffff 1.5 mbytes user mat sh74593 appendix d r01ds0186ej0120 rev.01.20 page 17 of 35 sep 10, 2012 appendix d.2 12.1 overview ? programming/erasing unit figure12.3 shows the block allocation of the user mat. h'0000 0000 h'0000 1fff h'0000 2000 h'0000 3fff h'0000 4000 h'0000 5fff h'0000 6000 h'0000 7fff h'0000 8000 h'0000 9fff h'0000 a000 h'0000 bfff h'0000 c000 h'0000 dfff h'0000 e000 h'0000 ffff h'0001 0000 h'0001 ffff h'0002 0000 h'0002 ffff h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff h'0006 0000 h'0006 ffff h'0007 0000 h'0007 ffff h'0008 0000 h'0008 ffff h'0009 0000 h'0009 ffff h'000a 0000 h'000b ffff h'000c 0000 h'000d ffff h'000e 0000 h'000f ffff h'fd80 0000 h'fd80 1fff h'fd80 2000 h'fd80 3fff h'fd80 4000 h'fd80 5fff h'fd80 6000 h'fd80 7fff h'fd80 8000 h'fd80 9fff h'fd80 a000 h'fd80 bfff h'fd80 c000 h'fd80 dfff h'fd80 e000 h'fd80 ffff h'fd81 0000 h'fd81 ffff h'fd82 0000 h'fd82 ffff h'fd83 0000 h'fd83 ffff h'fd84 0000 h'fd84 ffff h'fd85 0000 h'fd85 ffff h'fd86 0000 h'fd86 ffff h'fd87 0000 h'fd87 ffff h'fd88 0000 h'fd88 ffff h'fd89 0000 h'fd89 ffff h'fd8a 0000 h'fd8b ffff h'fd8c 0000 h'fd8d ffff h'fd8e 0000 h'fd8f ffff eb00 (8-kbyte) block name (size) eb01 (8-kbyte) eb02 (8-kbyte) eb03 (8-kbyte) eb04 (8-kbyte) eb05 (8-kbyte) eb06 (8-kbyte) eb07 (8-kbyte) eb08 (64-kbyte) eb09 (64-kbyte) eb10 (64-kbyte) eb11 (64-kbyte) eb12 (64-kbyte) eb13 (64-kbyte) eb14 (64-kbyte) eb15 (64-kbyte) eb16 (64-kbyte) eb17 (128-kbyte) eb18 (128-kbyte) eb19 (128-kbyte) sh74593 appendix d r01ds0186ej0120 rev.01.20 page 18 of 35 sep 10, 2012 appendix d.3 12.3.2 flash access status register (fastat) the fastat register indicates the access erro r status for the rom. if any bit in th e fastat register is set to "1", the fcu enters command-locked state (see section 12.8.3, error protection). to cancel a command-locked state, set the fastat register to h'10, and then issue a status-clear command to the fcu. flash access status register (fastat) sh74593 appendix d r01ds0186ej0120 rev.01.20 page 19 of 35 sep 10, 2012 bit abbreviation after reset r w description 4 cmdlk 0 r ? fcu command lock bit indicates whether the fcu is in command-locked state (see section 12.8.3, error protection). 0: the fcu is not in a command-locked state 1: the fcu is in a command-locked state [condition for clearing to "0"] ? the fcu completes the status-clear command processing while the fastat register is h'10. [condition for setting to "1"] ? the fcu detects an error and enters command-locked state. 3 to 0 ? all 0 0 0 reserved bits these bits are always read as "0". the write value should always be "0". note: * 1 writing a "0" after reading a "1" is only allowed in order to clear the flag. sh74593 appendix d r01ds0186ej0120 rev.01.20 page 20 of 35 sep 10, 2012 appendix d.4 12.3.6 flash p/e mode entry register (fentryr) the fentryr register specifies the p/e mode for the rom. writing to the fentryr register is enabled only when a specified value is written to the high-order byte. writing any other value initializes this register. to specify the p/e mode for the rom so that the fcu can accept commands, set either of bits fentry1 and fentry0 to "1". note that if this register is set to a value other than h'0001 or h'0002, the ilglerr bit in the fstatr0 register will be set to "1" and the fcu will switch to the command-locked state. the fentryr register can be initialized by a hardware rese t, or setting the freset bit in the fresetr register to "1". flash p/e mode entry register (fentryr) sh74593 appendix d r01ds0186ej0120 rev.01.20 page 21 of 35 sep 10, 2012 bit abbreviation after reset r w description 0 fentry0 0 r w rom p/e mode entry bit 0 these bits specify the p/e mode fo r the eb00 to eb19 blocks of rom (read addresses: h'0000 0000 to h'000f ffff; program/erase addresses: h'fd80 0000 to h'fd8f ffff). 0: the block of rom from eb00 to eb19 (1mbyte) is in read mode 1: the block of rom from eb00 to eb19 (1mbyte) is in p/e mode programming is enabled when the following conditions are all satisfied: ? the fwe bit in the fpmon register is "1". ? the frdy bit in the fstatr0 register is "1". ? h'aa is written to the fekey bit in word access. [conditions for clearing to "0"] ? the frdy bit in the fstatr0 register becomes "1" and the fwe bit in the fpmon register becomes "0". ? this register is written to in byte access. ? a value other than h'aa is written to the fekey bit in word access. ? "0" is written to the fentry0 bit while the write enabling conditions are satisfied. ? the fentryr register is written to while the fentryr register is not h'0000 and the write enabling conditions are satisfied. [condition for setting to "1"] ? "1" is written to fentry0 while the write enabling conditions are satisfied and the fentryr register is h'0000. sh74593 appendix d r01ds0186ej0120 rev.01.20 page 22 of 35 sep 10, 2012 appendix d.5 12.6.2 conditions for fcu command acceptance figure 12.6 is an fcu mode transition diagram. fentryr = h'0000 fentryr = h'0001 or fentryr = h'0002 rom read mode rom p/e mode figure 12.6 fcu mode transition diagram (rom-related modes) sh74593 appendix d r01ds0186ej0120 rev.01.20 page 23 of 35 sep 10, 2012 appendix d.6 12.6.2 conditions for fcu command acceptance (2) rom p/e mode fentryr = h'0001 or fentryr = h'0002 normal operation legend: : command input error termination command locked when set from the access miss state command miss or access miss h'50 status register clear h'20 erase h'e8 program h'80 data width program data input iterate 127 times input of 128 data items complete h'd0 verify program program operation h'd0 verify erase erase operation h'd0 verify lock bit read lock bit read operation h'71 lock bit read h'd0 verify lock bit program lock bit program operation h'77 lock bit program fentryr = h'0000 rom read mode rom p/e mode (command input wait) figure 12.7 command state transiti ons in rom read mode and p/e mode sh74593 appendix d r01ds0186ej0120 rev.01.20 page 24 of 35 sep 10, 2012 appendix d.7 12.6.3 fcu command usage (1) methods for switching to rom p/e mode write to fentryr specifies rom p/e mode. to set fentry1 to 1: write h'aa02. to set fentry0 to 1: write h'aa01. start end figure 12.8 procedure for transition to rom p/e mode sh74593 appendix d r01ds0186ej0120 rev.01.20 page 25 of 35 sep 10, 2012 appendix d.8 12.8.3 error protection table 12.7 error protection types error description ilglerr bit erserr bit prgerr bit fcuerr bit frdtct bit romae bit fentryr setting error the key code (h'aa) has been supplied as the upper 8 bits of the fentryr register but the value of the lower 8 bits is other than h'01 or h'02. 1 0 0 0 0 0 an undefined code has been specified in the first cycle of an fcu command. 1 0 0 0 0 0 the value specified in the last of the multiple cycles of an fcu command is not h'd0. 1 0 0 0 0 0 the value specified in the second cycle of a program command is not h'80. 1 0 0 0 0 0 illegal command error a command has been issued in command-locked state. 1 0/1 0/1 0/1 0/1 0/1 an error has occurred during erasure processing. 0 1 0 0 0 0 erasure error a block erase command has been issued for the erasure block whose lock bit is set to "0" while the fprotcn bit in the fprotr register is "0". 0 1 0 0 0 0 an error has occurred during programming processing. 0 0 1 0 0 0 programming error a program or lock bit program command has been issued for the erasure block whose lock bit is set to "0" while the fprotcn bit in the fprotr register is "0". 0 0 1 0 0 0 fcu error an error has occurred during cpu processing in the fcu. 0 0 0 1 0 0 a read access command has been issued to addresses h'fd90 0000 to h'fd97 ffff while fentry1 = "1" in rom p/e normal mode. 1 0 0 0 0 1 a read access command has been issued to addresses h'fd80 0000 to h'fd8f ffff while fentry0 = "1" in rom p/e normal mode. 1 0 0 0 0 1 an access command has been issued to addresses h'fd90 0000 to h'fd9f ffff while fentry1 = "0". 1 0 0 0 0 1 an access command has been issued to addresses h'fd80 0000 to h'fd8f ffff while fentry0 = "0". 1 0 0 0 0 1 a read access command has been issued to addresses h'0000 0000 to h'0017 ffff while the fentryr register value is not h'0000. 1 0 0 0 0 1 rom access error a rom programming or erasing command (program, lock bit program, or block erase command) has been issued while the user boot mat is selected. 1 0 0 0 0 1 an access command has been issued to an address other than the addresses for rom programming/erasure h'fd80 0000 to h'fd80 7fff while the user boot mat is selected. 1 0 0 0 0 1 sh74593 appendix e r01ds0186ej0120 rev.01.20 page 26 of 35 sep 10, 2012 appendix e section 13 superhyway ram (shwyram) 13.1 overview as shown in figure 13.2, the shwyram is allocated to the upper 512 kbytes of area 6 (h'1800 0000 to h'1807 ffff in the 29-bit physical address space). address (29-bit physical address) h'1800 0000 to h'1800 ffff h'1801 0000 to h'1801 ffff h'1802 0000 to h'1802 ffff h'1803 0000 to h'1803 ffff h'1804 0000 to h'1804 ffff h'1805 0000 to h'1805 ffff h'1806 0000 to h'1806 ffff h'1807 0000 to h'1807 ffff page page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 area 6 of p0/u0 area (64 mb) h'1800 0000 h'1800 0000 h'1807 ffff h'1808 0000 h'1bff ffff 32-bit virtual address space reserved (access not allowed) shwyram (512kb) h'1bff ffff area 6 of p1 area (64 mb) area 6 of p2 area (64 mb) area 6 of p3 area (64 mb) h'9800 0000 h'9bff ffff h'b800 0000 h'bbff ffff h'd800 0000 h'dbff ffff 29-bit physical address space (area 6) figure 13.2 address space sh74593 appendix f r01ds0186ej0120 rev.01.20 page 27 of 35 sep 10, 2012 appendix f section 14 clock generator (cpg) 14.1 overview table 14.1 lists the relation betwee n input frequency and input clock. table 14.1 relation between input frequency and input clock input frequency (mhz) pll frequency multiplier (input to cpu) cpu clock (mhz) shwy clock (mhz) peripheral clock (mhz) peripheral a clock (mhz) flexray clock (mhz) 20 12 240 80 40 80 80 sh74593 appendix g r01ds0186ej0120 rev.01.20 page 28 of 35 sep 10, 2012 appendix g section15 interrupt controller (intc) 15.5 interrupt response time table 15.9 shows the interrupt response time, which is the interval from when an interrupt request occurs until the interrupt exception handling is started and the start instruction of the interrupt handling is fetched. table 15.9 interrupt response time number of state item nmi irq peripheral module remarks priority determination time 7 pcyc 6 pcyc 5pcyc wait time until the cpu finishes the current sequence s-1 ( 0) icyc interval from when interrupt exception handling begins (saving sr and pc) until a shwy bus request is issued to fetch the start instruction of the interrupt handling 11icyc + 1scyc response time total (s + 10) icyc + 1scyc + 7 pcyc (s + 10) icyc + 1scyc + 6 pcyc (s + 10) icyc + 1scyc + 5pcyc minimum 55 icyc + s icyc 49 icyc + s icyc 43 icyc + s icyc when icyc:scyc: pcyc = 6 :2:1 legend: icyc: period for one cpu clock cycle scyc: period for one shwy clock cycle pcyc: period for one peripheral clock cycle s: number of instruct ion execution states sh74593 appendix h r01ds0186ej0120 rev.01.20 page 29 of 35 sep 10, 2012 appendix h section 28 direct ra m input interface (dri) appendix h.1 28.1 overview table 28.1 lists the overview of the drii modules. table 28.1 drii overview item description number of channels 3 channels operating frequency 80 mhz (when pack = 80 mhz) transfer method clock synchronous parallel input access areas all shwyram areas (up to 512 kbytes) maximum transfer rate 80 mbytes/second (wh en the drii operating frequency is 80 mhz) minimum data acquisition period the following are the minimum periods when the drii operating frequency is 80 mhz. 43.75 ns (special mode disabled and the input data bus width is 8 or 16 bits) 25 ns (special mode enabled) data acquisition bus width 8 or 16 bits event counter 16 bits 6 counters (dec5 to dec0) bank switching function two banks can be specif ied as the data storage destination in shwyram data acquisition edges either rising edges , falling edges, or both edges can be selected acquisition timing adjustment function sets the time between detection of the data acquisition edge and the acquisition operation decimation control function data can be acquired selectively using an event counter (dec5 to dec0) sh74593 appendix h r01ds0186ej0120 rev.01.20 page 30 of 35 sep 10, 2012 appendix h.2 28.3.23 drii address reload registers 0 and 1 (driiadr0rld and driiadr1rld) driiadr0ct and driiadr1ct are registers that hold counter reload values. when reload mode is selected with the drii transfer control register (driitrmcnt) admd (a ddress counter operating mode selection) bit, the corresponding drii address counters are reloaded with the values set in these registers when the drii data acquisition control register (driidcapcnt) dcpen (acquis ition enable) bit changes from "0" to "1". note: ? these registers may only be rewritten when the drii data acquisition control register (driidcapcnt) dcpen (acquisition enable) bit is in the "0" state. dri0 address reload register 0 (dri0adr0rld) dri1 address reload register 0 (dri1adr0rld) dri2 address reload register 0 (dri2adr0rld) sh74593 appendix h r01ds0186ej0120 rev.01.20 page 31 of 35 sep 10, 2012 appendix h.3 28.3.24 drii address counters 0 and 1 (driiadr0ct and driiadr1ct) the driiadr0ct and driiadr1ct counters are provided to specify bits a18 to a2 of the address in shwyram that is the drii module transfer destin ation. bits a31 to a19 are fixed at "0 ". these counters are incremented by "4" each time a drii transfer completes. there are two drii ad dress counter operating modes, and applications can select the mode with the drii transfer control register (dri itrmcnt) admd bit. see the documentation of the drii transfer control register (driitrmcnt) for details. notes: ? if a drii address counter value is a value other than an area in which shwyram is located, the drii module will behave as though the drii transfers comp lete, but no writes of the acquired data will be performed whatsoever. ? a drii address counter is incremented by "4" when a drii transfer completed. this is performed for the one that is active at that time according to the setting of the drii transfer cont rol register (driitrmcnt) adsl (address counter selection) bit. ? these registers must only be rewritten in the state where a drii transfer coun ter (driitrmct) underflow has occurred (the counter is stopped at the value h'0000 0000). dri0 address counters 0 (dri0adr0ct) dri1 address counters 0 (dri1adr0ct) dri2 address counters 0 (dri2adr0ct) sh74593 appendix i r01ds0186ej0120 rev.01.20 page 32 of 35 sep 10, 2012 appendix i section 29 direct ram output interface (dro) 29.1 overview table 29.1 lists the overview of the dro module. table 29.1 dro module overview item description transfer method parallel strobed output access area shwyram area ( 512 kbytes) output data width either 8-bits or 16-bits maximum transfer clock 10 mhz maximum transfer rate 20 mbytes/s (when 16 bits is selected, pck = 40mhz) strobe polarity either "h" active or "l" active may be selected. timing adjustment function the setup and hold times can be programmed in 1pck units relative to the strobe signal edge. interrupt request an interrupt request is generated afte r a prespecified number of data items have been output. sh74593 appendix j r01ds0186ej0120 rev.01.20 page 33 of 35 sep 10, 2012 appendix j section 38 electrical characteristics appendix j.1 38.1 absolute maximum ratings table 38.1 shows the absolute maximum ratings. table 38.1 absolute maximum ratings item symbol rating unit remarks v dd vdd ?0.3 to +2.0 v power supply voltage vcc, pllvcc vcc ?0.3 to +6.5 v input voltage vcc power supply related pins vin ?0.3 to vcc +0.3 v analog supply voltage avcc ?0.3 to +6.5 v avrefh ?0.3 to avcc +0.3 v analog reference voltage avrefl ?0.3 to avss +0.3 v avrefh > avrefl analog input voltage van ?0.3 to avcc +0.3 v vss ? pllvss ?0.1 to +0.1 v vss ? avss ?0.1 to +0.1 v vss differential voltage pllvss ? avss ?0.1 to +0.1 v digital input pins imax ?20 to +20 ma maximum input current per pin* 2 (per pin) analog input pins imax ?20 to +20 ma power dissipation pd 1200 mw ta = ?40c to + 105 c operating temperature* 1 topr ?40 to + 105 c storage temperature tstg ?55 to +125 c before assembly [usage notes] operating the mcu in excess of t he absolute maximum ratings may result in permanent damage. be sure to use the mcu in compliance with the connection of power pins, combination conditions of applicable power supply voltages, voltage applicable to each pin, and conditions of output voltage, as specified in the manual. connecting a non-specified power supply or using the mcu at an incorrect voltage may re sult in permanent damage of the mcu or the system that contains the mcu. notes: * 1 this does not guarantee that the micr ocomputer can operate continuously at 85c-plus. consult renesas if the microcomputer is going to be used for 85c-plus applications. * 2 ensure that the current input duration does not exceed 10 ms and that the total curr ent input does not exceed 100 ma. sh74593 appendix j r01ds0186ej0120 rev.01.20 page 34 of 35 sep 10, 2012 appendix j.2 section 38 electrical characteristics table 38.14 dc characteristics - supply current recommended operating conditions: vcc = pllvcc = 5.0 v 0.5 v/3.3 v 0.3 v, avcc = 5.0 v 0.5 v/3.3 v 0.3 v item symbol min. typ. max. unit measurement conditions core supply current (vdd power supply) i dd ? ? 560 ma ick = 240 mhz system consumption current (vcc power supply) * 1 (including flash memory programming and erasure) i cc ? ? 90 ma pck = 40 mhz pll supply current (pllvcc power supply) i pll ? ? 10 ma during a/d conversion ? ? 10 ma analog supply current (avcc power supply) awaiting a/d conversion i avcc ? ? 1 ma 2 modules, pck = 40mhz during a/d conversion ? ? 4 ma adc reference power supply current (avref) awaiting a/d conversion i avref ? ? 3.5 ma 2 modules, pck = 40mhz notes: * 1 an inrush current of about 100 ma will be caused at power on. ? when the a/d converter is not used, do not leave the avcc, avref, and avss pins open. ? the supply current is measured when v ih min = vcc ? 0.5 v, v il = 0.5 v, with all output pins unloaded. sh74593 appendix j r01ds0186ej0120 rev.01.20 page 35 of 35 sep 10, 2012 appendix j.3 section 38 electrical characteristics 38.3 ac characteristics ? the timing conditions without specifications are the following : vdd = 1.5 v + 0.15 v, -0.1 v, vcc = pllvcc = 5.0 v 0.5 v/3.3 v 0.3 v, avcc = 5.0 v 0.5 v/3.3 v 0.3 v, avrefh = 4.5 v to avcc/3.0 v to avcc, vss = pllvss = avss = avrefl = 0 v, ta = -40 c to + 105 c when not otherwise specified, the input threshold value is the value under conditions where all module input pins for the same channel are set to the same characteristics. when not otherwise specified, the output driving ability is the value under conditions where all module output pins for the same channel are set to the same characteristics. ? standard values are guaranteed when the output load capacity of the measurement pin is 15 pf to 50 pf. note that the output load capacity of the clkout pin is 15pf to 30pf. cl measured pin : clkout pin = 15 pf to 30 pf : other than the above = 15 pf to 50 pf cmos output figure 38.1 measurement circuit for output switching characteristics cmos input 0.8 vcc 0.2 vcc figure 38.2 input waveform and timing ch eck points at characteristics measurement cmos output note: ? for details on clkout output timing check points at characteristics measurement, refer to each figure in this section. 0.8 vcc 0.2 vcc figure 38.3 output timing check po ints at characteristics measurement all trademarks and registered trademarks are t he property of their respective owners. a - 1 revision history sh74593 datasheet description rev. date page summary 1.20 sep 10, 2012 - first edition issued general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2012 renesas electronics corporation. all ri g hts reserved . colo p hon 2. 0 |
Price & Availability of SH74593-15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |